(1) Field of the Invention
The present invention relates in general to wireless communications systems and more specifically to a method and apparatus for reducing the power consumption of an RF amplifier during transmission periods without significantly reducing any performance goals for the communications systems.
(2) Description of the Related Art
Digital communications devices including digital voice, for example digital cellular phones, and digital data such as computer networking transmit RF energy to communicate. These devices often require highly linear RF power amplifiers to operate properly. In general, linear power amplifiers consume much more power to operate compared to non-linear power amplifiers and are much less efficient.
Normally, the linear amplifiers used in these applications are Class A amplifiers. Class A amplifiers have a theoretical efficiency of fifty percent, however, a Class A amplifier used as a power amplifier typically operates at ten to twenty percent efficiency in order to maintain third-order intermodulation distortion down to required levels for most communications applications.
Traditionally, non-linear amplifiers are used to save power. However, the need for using linear power amplifiers has grown tremendously in the recent years as a result of the growth in digital communications technologies. Linear amplifiers are needed when a clean signal with minimal distortion is desired. Many small, hand-held digital electronic communication devices are battery powered, having limited power storage capacities. Therefore, it is desirable to increase the transmitter power efficiency, especially when linear RF power amplification is a requirement.
Traditionally, analog techniques were used as a means to develop control circuits that help reduce Class A amplifier power consumption. Usually, the voltage or power waveform entering or leaving the power amplifier is sampled and a control voltage waveform (error signal) is produced. The control waveform is then used to modulate (raise or lower) the DC supply output voltage of the power amplifier as needed. In effect, the supply voltage is varied in proportion to amplitude of the signal being amplified and DC supply voltage excess is reduced. When the DC supply excess is reduced, the amplifier average power consumption is also reduced.
There are several drawbacks to the traditional power saving methods. First, analog feedback and feed-forward control systems are difficult to manufacture in high yields and are therefore not cost effective in high volume production. Second, modulation of the DC supply voltage is complicated, circuit wise, and does not lend itself to easy implementation. Further, modulated power supplies are generally switching power supplies that are bulky (inductive component) and require additional low pass filtering to remove the unwanted switching frequency signals. Low pass filtering also places an upper limit on the modulation (signal) speed and response time for which the technique can operate. Third, the accuracy of the amplifier voltage signal or power signal measurement technique may vary with temperature or have limited dynamic range. And finally, DC power supply and RF amplifiers are normally highly integrated circuit xe2x80x98blocksxe2x80x99 that are developed independently which makes the adaptation of one xe2x80x98blockxe2x80x99 to the other xe2x80x98blockxe2x80x99 difficult to achieve for high yield and volume production applications. Therefore, a need exists for a less complicated alternative method to reduce the power consumption of Class A, RF power amplifiers that is more suited for high volume, high yielding commercial applications.
It is an object of the present invention to reduce the average power consumption of a highly linear RF power amplifier during transmission periods without significantly degrading the RF system performance objectives.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of instrumentalities and combinations particularly pointed out in the appended claims.
The invention describes a method and an apparatus that makes use of digital signal processing techniques to analyze digital (modulation) data as discrete sequences or discrete samples (sets) and then to set an optimum RF amplifier bias setting for each sequence that is determined either by utilizing an appropriate algorithm (computation) or by selection of a predefined bias setting (look-up table). The time interval for each discrete RF amplifier bias setting is chosen to correspond directly or indirectly with an associated (modulated) digital data sample set time interval.
The apparatus operates by dividing or fragmenting long sequences (quasi-continuous) of (modulation) data waveform (n-bit) samples into discrete blocks of short sequence data waveform (n-bit) samples. Each discrete block of (n-bit) samples has an associated magnitude characteristic (statistical quantity) that can be independent of the magnitude characteristic for the entire xe2x80x98longxe2x80x99 sequence. For example, the peak magnitude of the xe2x80x98longxe2x80x99 sequence may be much greater than the peak magnitude of a given short sequence fragment. The apparatus operates by saving or buffering the maximum magnitude characteristic of each short sequence for a predetermined length of time (delay). The continuous magnitude sampling within each short sequence is sequential, therefore, the buffered magnitude data is regularly updated (data clock) until the end of the short interval is reached.
The magnitude buffering operation during each short sequence creates a control delay time interval equal to the short sequence time interval (minimum). Therefore, the data waveform (n-bit) samples must also be delayed for a short sequence time interval to maintain synchronous behavior (delays) between the digital control processing and digital data processing paths. The digital data processing delay is implemented with a mux-demux, (parallel) data-buffering scheme that creates a single short sequence time delay function.
Once the buffered data and control (data magnitude) operations for a single short time interval (sample sequence) is completed, the data segment is forwarded on directly for upconversion, amplification, and filtering (transmitter). The control (data magnitude) information is used to either compute (algorithm) or map (look-up table) a control signal via an Analog-to-Digital Converter to the bias network of the RF amplifier in order to vary the bias. Furthermore, the lookup table or algorithm may also consider other related factors such as the modulation encoding, ambient temperature, or transmit signal quality desired
The method of the present invention comprises the steps of detecting the peak of each symbol, selecting an appropriate bias point, and then adjusting the bias to the appropriate bias point.
Among those benefits and improvements that have been disclosed, other objects and advantages of this invention will become apparent from the following description taken in conjunction with the accompanying drawings. The drawings constitute a part of this specification and include exemplary embodiments of the present invention and illustrate various objects and features thereof.